3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
DB), and Thin Shrink Small-Outline (PW)
Packages, and Standard Plastic 300-mil
DIPs (NT)

description
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements.
The device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to
disable the device so that the buses are effectively isolated.
The 74AC11245 is characterized for operation from –40°C to 85°C.