Features
■ Pin- and function-compatible with CY7C109B/CY7C1009B
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 80 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 3 mA
■ 2.0 V Data Retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE1, CE2 and OE options
■ CY7C109D available in Pb-free 32-pin 400-Mil wide Molded SOJ and 32-pin TSOP I packages. CY7C1009D available in Pb-free 32-pin 300-Mil wide Molded SOJ package

Functional Description
The CY7C109D/CY7C1009D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers.The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when:
■ Deselected (CE1 HIGH or CE2 LOW),
■ Outputs are disabled (OE HIGH),
■ When the write operation is active (CE1 LOW, CE2 HIGH, and WE LOW)
Write to the device by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).
Read from the device by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins.
The CY7C109D/CY7C1009D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives.
For a complete list of related documentation, click here.