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SN74ACT7803 数据表 (PDF) - Texas Instruments

SN74ACT7803 Datasheet PDF - Texas Instruments
部件名 SN74ACT7803
下载  SN74ACT7803 下载
文件大小   327.02 Kbytes
  17 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ACT7803 Datasheet (PDF)

Go To PDF Page 下载 数据表
SN74ACT7803 Datasheet PDF - Texas Instruments

部件名 SN74ACT7803
下载  SN74ACT7803 Click to download

文件大小   327.02 Kbytes
  17 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ACT7803 数据表 (HTML) - Texas Instruments


SN74ACT7803 产品详情

Member of the Texas Instruments
WidebusE Family
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
Read and Write Operations Synchronized
to Independent System Clocks
Input-Ready Flag Synchronized to Write
Clock
Output-Ready Flag Synchronized to Read
Clock
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width
Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates up to 67 MHz
Pin-to-Pin Compatible With SN74ACT7805
and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing

description
The SN74ACT7803 is a 512-word × 18-bit FIFO
suited for buffering asynchronous datapaths up to
67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering
without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output
edge control (OECE) circuit, dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be
reset upon power up.
The SN74ACT7803 is characterized for operation from 0°C to 70°C.




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