Contains Four Flip-Flops With Double-Rail
Outputs
Buffered Clock and Direct Clear Inputs
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators

description
This positive-edge-triggered flip-flop utilizes TTL
circuitry to implement D-type flip-flop logic with a
direct clear (CLR) input. Information at the data
(D) inputs meeting setup-time requirements is
transferred to outputs on the positive-going edge
of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When the clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output.