FEATURES
• Available in the Texas Instruments NanoFree™
Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.6 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• I off Supports Live Insertion, Partial-Power- Down Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to
Translate Inputs From a Max of 5.5 V Down to
the V CC Level
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)

DESCRIPTION
This dual buffer driver is designed for 1.65-V to 5.5-V
VCC operation.
The SN74LVC2G240 device is designed specifically
to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-
oriented receivers and transmitters.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is organized as two 1-bit buffers/drivers
with separate output-enable (OE) inputs. When OE is
low, the device passes data from the A input to the Y
output. When OE is high, the outputs are in the high-
impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.