features
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
Wide Analog Input: 0 V to AVDD
Differential Nonlinearity Error: < ± 0.5 LSB
Integral Nonlinearity Error: < ± 0.5 LSB
Single 2.7-V to 5.5-V Supply Operation
Low Power: 12 mW at 3 V and 35 mW at 5 V
Auto Power Down of 1 mA Max
Software Power Down: 10 mA Max
Internal OSC
Hardware Configurable
DSP and Microcontroller Compatible
Parallel Interface
Binary/Twos Complement Output
Hardware Controlled Extended Sampling
Hardware or Software Start of Conversion

applications
Mass Storage and HDD
Automotive
Digital Servos
Process Control
General-Purpose DSP
Image Sensor Processing

description
The TLV571 is an 8-bit data acquisition system
that combines a high-speed 8-bit ADC and a
parallel interface. The device contains two on-chip control registers allowing control of software conversion start
and power down via the bidirectional parallel port. The control registers can be set to a default mode using a
dummy RD while WR is tied low allowing the registers to be hardware configurable.
The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to
AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only
12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that
automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10 mA.
Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal
choice for high-speed digital signal processing.