1FEATURES
2• >300 Mbps Dual Link Raw Throughput
• MPL Physical Layer (MPL-0)
• Pin Selectable Master / Slave Mode
• Frequency Reference Transport
• Complete LVCMOS / MPL Translation
• Interface Modes:
– 16-bit CPU, i80 or m68 Style
– RGB565 with Glue Logic
• −30°C to 85°C Operating Range
• Link Power Down Mode Reduces I DDZ < 10 μA
• Dual Display Support (CS1* & CS2*)
• Via-less MPL Interconnect Feature
• 3.0V Supply Voltage (VDD and VDDA)
• Interfaces to 1.7V to 3.3V Logic (VDDIO)

SYSTEM BENEFITS
• Small Interface
• Low Power
• Low EMI
• Frequency Reference Transport
• Intrinsic Level Translation

DESCRIPTION
The LM2502 device is a dual link display interface
SERDES that adapts existing CPU / video busses to
a low power current-mode serial MPL link. The
chipset may also be used for a RGB565 application
with glue logic. The interconnect is reduced from 22
signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost.
The Master Serializer (SER) resides beside an
application processor or baseband processor and
translates a parallel bus from LVCMOS levels to
serial MPL levels for transmission over a flex cable
and PCB traces to the Slave Deserializer (DES)
located near the display module.
Dual display support is provided for a primary and
sub display through the use of two ChipSelect
signals. A Mode pin selects either a i80 or m68 style
interface.
The Power_Down (PD*) input controls the power
state of the MPL interface. When PD* is asserted, the
MD1/0 and MC signals are powered down to save
current.
The LM2502 implements the physical layer of the
MPL Standard (MPL-0). The LM2502 is offered in
NOPB (Lead-free) NFBGA and WQFN packages.