1 Features
• 1.6Gbps to 2.5Gbps (Gigabits per second)
serializer/deserializer
• Hot-plug protection
• High-performance 68-pin ceramic quad flat pack
package (HFG)
• Low-power operation
• Programmable preemphasis levels on serial output
• Interfaces to backplane, copper cables, or optical
converters
• On-chip 8-bit/10-bit encoding/decoding, comma
detect
• On-chip PLL provides clock synthesis from lowspeed
reference
• Low power: < 500mW
• 3V tolerance on parallel data input signals
• 16-bit parallel TTL-compatible data interface
• Designed for high-speed backplane interconnect
and point-to-point data link
• Military temperature range (–55°C to 125°C Tcase)
• Loss-of-Signal (LOS) detection
• Integrated 50Ω termination resistors on RX
• Engineering evaluation (/EM) samples are
available 1

2 Applications
• Point-to-Point High-Speed I/O
• Data Acquisition
• Data Processing

3 Description
The TLK2711-SP is a member of the WizardLink
transceiver family of multigigabit transceivers,
intended for use in ultra-high-speed bidirectional
point-to-point data transmission systems. The
TLK2711-SP supports an effective serial interface
speed of 1.6Gbps to 2.5Gbps, providing up to 2Gbps
of data bandwidth.
The primary application of the TLK2711-SP is to
provide high-speed I/O data channels for point-topoint
baseband data transmission over controlled
impedance media of approximately 50Ω. The
transmission media can be printed circuit board,
copper cables, or fiber-optic cable. The maximum rate
and distance of data transfer is dependent upon the
attenuation characteristics of the media and the noise
coupling to the environment.
This device can also be used to replace parallel data
transmission architectures by providing a reduction in
the number of traces, connector pins, and transmit/
receive pins. Parallel data loaded into the transmitter
is delivered to the receiver over a serial channel,
which can be a coaxial copper cable, a controlled
impedance backplane, or an optical link. It is then
reconstructed into its original parallel format. It offers
significant power and cost savings over parallel
solutions, as well as scalability for higher data rates
in the future.
The TLK2711-SP performs parallel-to-serial and
serial-to-parallel data conversion. The clock extraction
functions as a physical layer (PHY) interface device.
The serial transceiver interface operates at a
maximum speed of 2.5Gbps. The transmitter latches
16-bit parallel data at a rate based on the supplied
reference clock (TXCLK). The 16-bit parallel data is
internally encoded into 20 bits using an 8-bit/10-bit
(8b/10b) encoding format. The resulting 20-bit word
is then transmitted differentially at 20× the reference
clock (TXCLK) rate. The receiver section performs
the serial-to-parallel conversion on the input data,
synchronizing the resulting 20-bit wide parallel data
to the recovered clock (RXCLK). It then decodes the
20-bit wide data using the 8-bit/10-bit decoding format
resulting in 16 bits of parallel data at the receive data
pins (RXD0–RXD15). The outcome is an effective
data payload of 1.28Gbps to 2Gbps (16 bits data ×
the frequency).
The TLK2711-SP is available in a 68-pin ceramic
nonconductive tie-bar package (HFG).