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TLV5619 数据表 (PDF) - Texas Instruments

TLV5619 Datasheet PDF - Texas Instruments
部件名 TLV5619
下载  TLV5619 下载
文件大小   927.53 Kbytes
页   27 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 2.7VTO05.5V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

TLV5619 Datasheet (PDF)

Go To PDF Page 下载 数据表
TLV5619 Datasheet PDF - Texas Instruments

部件名 TLV5619
下载  TLV5619 Click to download

文件大小   927.53 Kbytes
页   27 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 2.7VTO05.5V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

TLV5619 数据表 (HTML) - Texas Instruments


TLV5619 产品详情

Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Single Supply 2.7-V to 5.5-V Operation
±0.4 LSB Differential Nonlinearity (DNL),
±1.5 LSB Integral Nonlinearity (INL)
12-Bit Parallel Interface
Compatible With TMS320 DSP
Internal Power On Reset
Settling Time 1 μs Typ
Low Power Consumption:
− 8 mW for 5-V Supply
− 4.3 mW for 3-V Supply
Reference Input Buffers
Voltage Output
Monotonic Over Temperature
Asynchronous Update

applications
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial
Controls
Machine and Motion Control Devices
Cordless and Wireless Telephones
Speech Synthesis
Communication Modulators
Arbitrary Waveform Generation

description
The TLV5619 is a 12-bit voltage output DAC with a microprocessor and TMS320 compatible parallel interface.
The 12 data bits are double buffered so that the output can be updated asynchronously using the LDAC pin.
During normal operation, the device dissipates 8 mW at a 5-V supply and 4.3 mW at a 3-V supply. The power
consumption can be lowered to 50 nW by setting the DAC to power-down mode.
The output voltage is buffered by a ×2 gain rail-to-rail amplifier, which features a Class A output stage to improve
stability and reduce settling time.




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