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TPS3836 数据表 (PDF) - Texas Instruments

TPS3836 Datasheet PDF - Texas Instruments
部件名 TPS3836
下载  TPS3836 下载
文件大小   953.45 Kbytes
  17 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 NANOPOWER SUPERVISORY CIRCUITS

TPS3836 Datasheet (PDF)

Go To PDF Page 下载 数据表
TPS3836 Datasheet PDF - Texas Instruments

部件名 TPS3836
下载  TPS3836 Click to download

文件大小   953.45 Kbytes
  17 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 NANOPOWER SUPERVISORY CIRCUITS

TPS3836 数据表 (HTML) - Texas Instruments


TPS3836 产品详情

1FEATURES
· ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
· Supply Current of 220 nA (Typ)
· Precision Supply Voltage Supervision Range:
1.8 V, 2.5 V, 3 V, 3.3 V
· Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
· Push/Pull RESET Output (TPS3836), RESET
Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
· Manual Reset
· 5-Pin SOT-23 Package

SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
· Controlled Baseline
· One Assembly/Test Site
· One Fabrication Site
· Available in Military (–55°C/125°C)
Temperature Range(1)
· Extended Product Life Cycle
· Extended Product-Change Notification
· Product Traceability

APPLICATIONS
· Applications Using Automotive Low-Power
DSPs, Microcontrollers, or Microprocessors
· Battery-Powered Equipment
· Intelligent Instruments
· Wireless Communication Systems
· Automotive Systems
(1) Custom temperature ranges available

DESCRIPTION
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing
supervision, primarily for digital signal processing (DSP) and processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold
voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after VDD has risen above VIT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the
delay time is typically 200 ms.




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