Product Features
• Fully compliant with JEDEC e·MMC 5.1 Standard (JESD84-B51)
• 153-ball BGA, 0.5mm pitch, 11.5 x 13mm, RoHS compliant
• 3D TLC NAND base technology
• Multiple 3D TLC or enhanced/reliable mode partitions user configurable according to e·MMC Spec 5.1
• High performance e·MMC 5.1 specification
o Eleven-wire bus (clock, Data Strobe, 1 bit command, 8 bit data bus) and a hardware reset
o Three different data bus width modes: 1-bit (default), 4-bit, and 8-bit
o Clock frequencies 0-200MHz, High Speed Mode HS400
o Command Queue Feature according to e·MMC Spec 5.1
o Up to 300MB/s sequential read and up to 230MB/s sequential write
• Power Supply: (Low-power CMOS technology)
o VCCQ 1.7V to 1.95V or 2.7V to 3.6V e·MMC supply / VCC 2.7V to 3.6V NAND Flash supply
• Optimized FW algorithms
o Power-fail data loss protection
o Wear Leveling technology Equal wear leveling of static and dynamic data. The wear leveling assures that dynamic data as well as static data is balanced evenly across the memory. With that the maximum write endurance of the device is ensured
o Read Disturb Management The read commands per region are monitored and the content is conditionally refreshed when critical levels have occurred
o Auto Read Refresh The interruptible background process maintains the user data for Read Disturb effects or Retention degradation due to high temperature effects
o Diagnostic features with Device Health Report according to e·MMC Spec 5.1, and detailed Lifetime Monitor data (Alliance proprietary, accessible through standard e·MMC commands).
o Field Firmware update2 according to e·MMC Spec 5.1
o Discard and Sanitize, Trim
o Boot Operation Mode and Alternative Boot Operation Mode
o Replay Protected Memory Block (RPMB)

Product Description
The Alliance e·MMC is a managed non-volatile storage consisting of a single chip MMC controller and a NAND flash memory chip inside a JEDEC defined standard BGA package. It is specially designed as a small form factor memory product for storage of data and as a boot media. The performance is optimized to a mostly read operation mode at low power consumption. The utilization of 3D TLC NAND technology, with the option to configure the memory in Enhanced mode (pSLC), targets higher demanding industrial, which is supported by the industrial temperature grade specification.
The e·MMC controller directly manages NAND flash, including ECC, wear-leveling, IOPS optimization and read sensing. The firmware features support high throughput for large data transfers and performance for small random data more commonly found in code usage. It also contains several security features as well as multiple boot partitions. Uses advanced refresh features for retention optimization for read intensive applications.
e·MMC communication is based on an advanced 11-signal bus. The communication protocol is defined as a part of the JEDEC e·MMC standard and referred to as the e·MMC mode.