FEATURES
 Flexible & Efficient Memory
Architecture
- Organization: 512Mb x8
- Memory Cell Array: (512M + 16M) x 8bit
- Data Register: (2K + 64) x 8bit
- Page Size: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
- Memory Cell: 1bit/Memory Cell
 Highest performance
- Read Performance
- Random Read: 25us (Max.)
- Serial Access: 25ns (Max.)
- Write Performance
- Program time: 300us - typical
- Block Erase time: 3ms – typical
 Low Power with Wide Temp. Ranges
- Single 3.3V (2.7V to 3.6V) Voltage
Supply
- 10 mA Active Read Current
- 8 μA Standby Current
- Temp Grades:
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
- Automotive, A1: -40°C to +85°C
- Automotive, A2: -40°C to +105°C
 Reliable CMOS Floating Gate
Technology
- ECC Requirement: X8 - 4bit/512Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
 Efficient Read and Program modes
- Command/Address/Data Multiplexed I/O
Interface
- Command Register Operation
- Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
- NOP: 4 cycles
- Cache Program Operation for High
Performance Program
- Cache Read Operation
- Copy-Back Operation
- EDO mode
- Two-Plane Operation
- Bad-Block-Protect
 Advanced Security Protection
- Hardware Data Protection
- Program/Erase Lockout during Power
Transitions
 Industry Standard Pin-out & Packages
- T =48-pin TSOP 1