1.2 Features
The TSB82AA2B device supports the following features:
• Single 3.3-V Supply (1.8-V Internal Core Voltage With Regulator)
• Available in Industrial (−40°C to 85°C) and Commercial (0°C to 70°C) Temperature Ranges
• 3.3-V and 5-V PCI Signaling Environments
• Serial Bus Data Rates of 100M bit/s, 200M bit/s, 400M bit/s, and 800M bit/s
• Physical Write Posting of up to Three Outstanding Transactions
• Serial ROM or Boot ROM Interface Supports 2-Wire Serial EEPROM Devices
• 33-MHz/64-Bit and 33-MHz/32-Bit Selectable PCI Interface
• Multifunction Terminal (MFUNC Terminal 1)
− PCI_CLKRUN Protocol Per PCI Mobile Design Guide
− General-Purpose I/O (GPIO)
− CYCLEIN/CYCLEOUT for External Cycle Timer Control for Customized Synchronization
• PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency
− Transmit FIFO — 5K Asynchronous
− Transmit FIFO — 2K Isochronous
− Receive FIFO — 2K Asynchronous
− Receive FIFO — 2K Isochronous
• D0, D1, D2, and D3 Power States and PME Events Per PCI Bus Power-Management Interface
Specification
• Programmable Asynchronous Transmit Threshold
• Isochronous Receive Dual-Buffer Mode
• Out-of-Order Pipelining for Asynchronous Transmit Requests
• Register Access Fail Interrupt When PHY SYSCLK Is Not Active
• Initial Bandwidth Available and Initial Channels Available Registers
• Digital Video and Audio Performance Enhancements
• Fabricated in Advanced Low-Power CMOS Process
• Packaged in 144-Terminal LQFP (PGE)