Features
• C Compiler Optimized RISC Architecture
• Operating Speed:
– DC – 64 MHz clock input
– 62.5 ns minimum instruction cycle
• Six Direct Memory Access (DMA) Controllers:
– Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR
spaces
– User programmable source and destination sizes
– Hardware and software triggered data transfers
• Vectored Interrupt Capability:
– Selectable high/low priority
– Fixed interrupt latency of three instruction cycles
– Programmable vector table base address
– Backwards compatible with previous interrupt capabilities
• 127-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
– Watchdog Reset on too long or too short interval between watchdog clear events
– Variable prescaler selection
– Variable window size selection