Features
32-bit Arm Cortex-M3 Core
◼Processor version: r2p1
◼Up to 144 MHz Frequency Operation
◼Memory Protection Unit (MPU): improves the reliability of an
embedded system
◼Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
◼24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash
memories.
◼MainFlash
 Up to 512 Kbyte
 Built-in Flash Accelerator System with 16 Kbyte trace
buffer memory
 The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
 Security function for code protection
◼WorkFlash
 32 Kbyte
 Read cycle
 4wait-cycle: the operation frequency more than 72 MHz
 2wait-cycle: the operation frequency more than 40 MHz,
and to 72 MHz
 0wait-cycle: the operation frequency to 40 MHz
 Security function is shared with code protection
[SRAM]
This Series contain a total of up to 64 Kbyte on-chip SRAM.
This is composed of two independent SRAM (SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
◼SRAM0: Up to 32 Kbyte
◼SRAM1: Up to 32 Kbyte
External Bus Interface
◼Supports SRAM, NOR and NAND Flash device
◼Up to 8 chip selects
◼8-/16-bit Data width
◼Up to 25-bit Address bit
◼Maximum area size: Up to 256 Mbytes
◼Supports Address/Data multiplex
◼Supports external RDY input
USB Interface
USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
◼USB device
 USB2.0 Full-Speed supported
 Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
• EndPoint 3 to 5 can be selected Bulk-transfer or
Interrupt-transfer
• EndPoint 1 to 5 is comprised Double Buffer
• The size of each EndPoint is as follows.
• EndPoint 0, 2 to 5: 64 bytes
• EndPoint 1: 256 bytes
◼USB host
 USB2.0 Full/Low-speed supported
 Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
 USB Device connected/dis-connected automatically detect
 IN/OUT token handshake packet automatically
 Max 256-byte packet-length supported
 Wake-up function supported
CAN Interface (Max two channels)
◼ Compatible with CAN Specification 2.0A/B
◼ Maximum transfer rate: 1 Mbps
◼ Built-in 32 message buffer