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H9TQ17ABJTCC 数据表 (PDF) - Hynix Semiconductor

H9TQ17ABJTCC Datasheet PDF - Hynix Semiconductor
部件名 H9TQ17ABJTCC
下载  H9TQ17ABJTCC 下载
文件大小   3542.11 Kbytes
  183 Pages
制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor
功能描述 16GB eNAND (x8) 16Gb LPDDR3 (x32)

H9TQ17ABJTCC Datasheet (PDF)

Go To PDF Page 下载 数据表
H9TQ17ABJTCC Datasheet PDF - Hynix Semiconductor

部件名 H9TQ17ABJTCC
下载  H9TQ17ABJTCC Click to download

文件大小   3542.11 Kbytes
  183 Pages
制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor
功能描述 16GB eNAND (x8) 16Gb LPDDR3 (x32)

H9TQ17ABJTCC 数据表 (HTML) - Hynix Semiconductor


H9TQ17ABJTCC 产品详情

FEATURES
[ CI-MCP ]
● Operation Temperature
- (-25)oC ~ 85oC
● Package
- 221-ball FBGA - 11.5x13.0mm2, 1.0t, 0.5mm pitch
- Lead & Halogen Free
[ e-NAND ]
• eMMC5.0 compatible
(Backward compatible to eMMC4.5)
• Bus mode
- Data bus width : 1 bit(default), 4 bits, 8 bits
- Data transfer rate: up to 400MB/s (HS400)
- MMC I/F Clock frequency : 0~200MHz
- MMC I/F Boot frequency : 0~52MHz
• Operating voltage range
- Vcc (NAND) : 2.7 - 3.6V
- Vccq (Controller) : 1.7 - 1.95V / 2.7 - 3.6V
• Temperature
- Operation (-25℃ ~ +85℃)
- Storage without operation (-40℃ ~ +85℃)
• Others
- This product is compliance with the RoHS
directive
• Supported features
- HS400, HS200
- HPI, BKOPS
- Packed CMD, Cache
- Partitioning, RPMB
- Discard, Trim, Erase, Sanitize
- Write protect, Lock / Unlock
- PON, Sleep / Awake
- Reliable write
- Boot feature, Boot partition
- HW / SW Reset
- Field firmware update
- Configurable driver strength
- Health(Smart) report
- Production state awareness
- Secure removal type
[ LPDDR3 ]
 VDD1 = 1.8V (1.7V to 1.95V)
 VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
 HSUL_12 interface (High Speed Unterminated Logic 1.2V)
 Double data rate architecture for command, address and
data Bus;
- all control and address except CS_n, CKE latched at both
rising and falling edge of the clock
- CS_n, CKE latched at rising edge of the clock
- two data accesses per clock cycle
 Differential clock inputs (CK_t, CK_c)
 Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
- Data outputs aligned to the edge of the data strobe
(DQS_t, DQS_c) when READ operation
- Data inputs aligned to the center of the data strobe
(DQS_t, DQS_c) when WRITE operation
 DM masks write data at the both rising and falling edge of
the data strobe
 Programmable RL (Read Latency) and WL (Write Latency)
 Programmable burst length: 8
 Auto refresh and self refresh supported
 All bank auto refresh and per bank auto refresh supported
 Auto TCSR (Temperature Compensated Self Refresh)
 PASR (Partial Array Self Refresh) by Bank Mask and Segment
Mask
 DS (Drive Strength)
 DPD (Deep Power Down)
 ZQ (Calibration)
 ODT (On Die Termination)





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关于 Hynix Semiconductor


Hynix Semiconductor是一家韩国公司,专门从事内存半导体的设计和制造。
该公司成立于1983年,总部位于韩国伊歇。
Hynix是世界上领先的DRAM(动态随机访问存储器)和NAND闪存的生产商之一,它们用于各种应用程序,例如计算机系统,移动设备和固态驱动器。
Hynix以其在内存半导体技术方面的专业知识以及为客户提供高质量和高性能存储产品的能力。
该公司在世界各地拥有运营和设施,并与客户紧密合作,提供满足其特定需求和需求的定制内存解决方案。
除了其内存产品外,Hynix还为汽车和数据中心市场提供了一系列产品和解决方案,例如System-A-A-Chip(SOC)产品(SOC)产品和高带宽内存(HBM)产品。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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