Features
• LS1046A has four cores and LS1026A has two cores
• Four 32-bit/64-bit Arm® Cortex®-v8 A72 CPUs
– Arranged as a single cluster of four cores sharing a single 2 MB L2 cache
– Up to 1.8 GHz operation
– Single-threaded cores with 32 KB L1 data cache and 48 KB L1 instruction cache
• Hierarchical interconnect fabric
– Up to 700 MHz operation
• One 32-bit/64-bit DDR4 SDRAM memory controller with ECC and interleaving support
– Up to 2.1 GT/s
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution (FMan)
– Queue management for scheduling, packet sequencing, and congestion management (QMan)
– Hardware buffer management for buffer allocation and de-allocation (BMan)
– Cryptography acceleration (SEC)
– IEEE 1588™ support
• Two RGMII interfaces
• Eight SerDes lanes for high-speed peripheral interfaces
– Three PCI Express 3.0 controllers
– One Serial ATA (SATA 6 Gbit/s) controller
– Up to two XFI (10 GbE) interfaces
– Up to five SGMII interfaces supporting 1000 Mbps
– Up to three SGMII interfaces supporting 2500 Mbps
– Up to one QSGMII interface
– Supports 10GBase-KR
– Supports 1000Base-KX
• Additional peripheral interfaces
– One Quad Serial Peripheral Interface (QSPI) controller
– One Serial Peripheral Interface (SPI) controller
– Integrated flash controller (IFC) supporting NAND and NOR flash
– Three high-speed USB 3.0 controllers with integrated PHY
– One Enhanced Secure Digital Host Controller supporting SD 3.0, eMMC 4.4, and eMMC 4.5
– Four I2C controllers
– Two 16550-compliant DUARTs and six low-power UARTs (LPUARTs)
– General purpose IO (GPIO), eight Flextimers
– One Queue Direct Memory Access Controller (qDMA)
– One Enhanced Direct Memory Access Controller (eDMA)
– Global programmable interrupt controller (GIC)
– Thermal monitoring unit (TMU)
• 780 FC-PBGA package, 23 mm x 23 mm