DESCRIPTION
The M36W108 is multi-chip device containing an 8 Mbit boot block Flash memory and a 1 Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0 mm ball pitch and LGA48 1.0 mm land pitch.

■ M36W108T and M36W108B are replaced respectively by the M36W108AT and M36W108AB
■ SUPPLY VOLTAGE
    – VCCF = VCCS = 2.7V to 3.6V: for Program, Erase and Read
■ ACCESS TIME: 100ns
■ LOW POWER CONSUMPTION
    – Read: 40mA max. (SRAM chip)
    – Stand-by: 30µA max. (SRAM chip)
    – Read: 10mA max. (Flash chip)
    – Stand-by: 100µA max. (Flash chip)

FLASH MEMORY
■ 8 Mbit (1Mb x 8) BOOT BLOCK ERASE
■ PROGRAMMING TIME: 10µs typical
■ PROGRAM/ERASE CONTROLLER (P/E.C.)
    – Program Byte-by-Byte
    – Status Register bits and Ready/Busy Output
■ MEMORY BLOCKS
    – Boot Block (Top or Bottom location)
    – Parameter and Main Blocks
■ BLOCK, MULTI-BLOCK and CHIP ERASE
■ ERASE SUSPEND and RESUME MODES
    – Read and Program another Block during Erase Suspend
■ 100,000 PROGRAM/ERASE CYCLES per BLOCK
■ ELECTRONIC SIGNATURE
    – Manufacturer Code: 20h
    – Device Code, M36W108T: D2h
    – Device Code, M36W108B: DCh

SRAM
■ 1 Mbit (128Kb x 8)
■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS
■ LOW VCC DATA RETENTION: 2V