▪ Distribution, fanout, phase-delay of clock, and SYSREF signals
▪ Low output noise floor: -163dBc/Hz (245.76MHz)
▪ Supports clock frequencies up to 3GHz, including
clock output frequencies of 983.04MHz,
491.52MHz, 245.76MHz, and 122.88MHz
▪ Phase alignment mode across multiple buffers with any frequency divider setting
▪ Configuration through 3-wire SPI interface
▪ Supply voltage:
• 3.3V core and signal I/O
• 1.8V digital control SPI I/O (3.3V-tolerant inputs)
▪ Reference inputs are fail-safe
▪ Provides four output channels with a total of 16
differential outputs
▪ Outputs channels include:
• Dedicated clock outputs
• Outputs configurable as SYSREF outputs with
individual phase delay stages, or configurable as
additional clock outputs
• Clock outputs are powered-on/enabled at startup
• QREF_r (SYSREF) outputs disabled at startup
▪ Each clock channel contains:
• Frequency Dividers: ÷1, ÷2, ÷3, ÷4, ÷6, ÷8, ÷12,
÷16, ÷24
• Clock phase delay circuits, delay unit is the clock
period; 256 steps
▪ SYSREF: Configurable precision phase delay
circuits: 8 steps of 131ps, 262ps, 393ps, or 524ps
▪ Flexible differential outputs:
• LVDS/LVPECL/AC-HCSL
• Amplitude configurable for LVDS and LVPECL
• Power-down modes for unused outputs
• Supports DC and AC coupling
• QREF_r (SYSREF) output pre-bias feature to
prevent glitches when turning output on or off
▪ Package: 64-VFQFPN (9.0 × 9.0 × 0.85 mm)
▪ Ambient temperature range: -40°C to +105°C (case)