▪ Four independent timing channels
• Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock
Loop (DPLL)
• DPLLs generate telecom compliant clocks
▪ Compliant with ITU-T G.8262 for Synchronous Ethernet
▪ Compliant with ITU-T G.8262.1 for enhanced
Synchronous Ethernet
▪ Compliant with legacy SONET/SDH and PDH
requirements
• DPLL Digital Loop Filters (DLFs) are programmable with cut
off frequencies from 0.09mHz to 12kHz
• DPLL/DCO channels share frequency information using the
Combo Bus to simplify compliance with ITU-T G.8273.2
• Switching between DPLL and DCO modes is hitless and dynamic
▪ Automatic reference switching between DCO and DPLL
modes to simplify support for an external phase/time input
interface in a T-BC
• Generates output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
• Each FOD supports output phase tuning with 1ps resolution