• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLKx, nPCLKx pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 310ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
10kHz - 20MHz: 100fs (maximum)
• Full 3.3V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFPN packaging
• -40°C to 85°C ambient operating temperature