[Luminary Micro, Inc.]

Architectural Overview

The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The LM3S808 microcontroller is targeted for industrial applications, including test and measurement equipment, factory automation, HVAC and building control, motion control, medical instrumentation, fire and security, and power/energy.

In addition, the LM3S808 microcontroller offers the advantages of ARMs widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.

Additionally, the microcontroller uses ARMs Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S808 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers precise needs.

Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network.

Product Features

The LM3S808 microcontroller includes the following product features:

■ 32-Bit RISC Performance

   – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications

   – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

   – Thumb®-compatible Thumb-2-only instruction set processor core for high code density

   – 50-MHz operation

   – Hardware-division and single-cycle-multiplication

   – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

   – 23 interrupts with eight priority levels

   – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality

   – Unaligned data access, enabling data to be efficiently packed into memory

   – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control

■ Internal Memory

   – 64 KB single-cycle flash

      • User-managed flash block protection on a 2-KB block basis

      • User-managed flash data programming

      • User-defined and managed flash-protection block

   – 8 KB single-cycle SRAM

■ General-Purpose Timers

   – Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timer/counters. Each GPTM can be configured to operate independently as timers or event counters: as a single 32-bit timer, as one 32-bit Real-Time Clock (RTC) to event capture, for Pulse Width Modulation (PWM), or to trigger analog-to-digital conversions

   – 32-bit Timer modes

      • Programmable one-shot timer

      • Programmable periodic timer

      • Real-Time Clock when using an external 32.768-KHz clock as the input

      • User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug

      • ADC event trigger

   – 16-bit Timer modes

      • General-purpose timer function with an 8-bit prescaler

      • Programmable one-shot timer

      • Programmable periodic timer

      • User-enabled stalling when the controller asserts CPU Halt flag during debug

      • ADC event trigger

   – 16-bit Input Capture modes

      • Input edge count capture

      • Input edge time capture

   – 16-bit PWM mode

      • Simple PWM mode with software-programmable output inversion of the PWM signal

■ ARM FiRM-compliant Watchdog Timer

   – 32-bit down counter with a programmable load register

   – Separate watchdog clock with an enable

   – Programmable interrupt generation logic with interrupt masking

   – Lock register protection from runaway software

   – Reset generation logic with an enable/disable

   – User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ Synchronous Serial Interface (SSI)

   – Master or slave operation

   – Programmable clock bit rate and prescale

   – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

   – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces

   – Programmable data frame size from 4 to 16 bits

   – Internal loopback test mode for diagnostic/debug testing

■ UART

   – Two fully programmable 16C550-type UARTs

   – Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading

   – Programmable baud-rate generator with fractional divider

   – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface

   – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

   – Standard asynchronous communication bits for start, stop, and parity

   – False-start-bit detection

   – Line-break generation and detection

■ ADC

   – Single- and differential-input configurations

   – Eight 10-bit channels (inputs) when used as single-ended inputs

   – Sample rate of 500 thousand samples/second

   – Flexible, configurable analog-to-digital conversion

   – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs

   – Each sequence triggered by software or internal event (timers, analog comparators, or GPIO)

   – On-chip temperature sensor

■ Analog Comparators

   – One integrated analog comparator

   – Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence

   – Compare external pin input to external pin input or to internal programmable voltage reference

■ I2C

   – Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode

   – Interrupt generation

   – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

■ GPIOs

   – 5-28 GPIOs, depending on configuration

   – 5-V-tolerant input/outputs

   – Programmable interrupt generation as either edge-triggered or level-sensitive

   – Bit masking in both read and write operations through address lines

   – Can initiate an ADC sample sequence

   – Programmable control for GPIO pad configuration:

      • Weak pull-up or pull-down resistors

      • 2-mA, 4-mA, and 8-mA pad drive

      • Slew rate control for the 8-mA drive

      • Open drain enables

      • Digital input enables

■ Power

   – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V

   – Low-power options on controller: Sleep and Deep-sleep modes

   – Low-power options for peripherals: software controls shutdown of individual peripherals

   – User-enabled LDO unregulated voltage detection and automatic reset

   – 3.3-V supply brown-out detection and reporting via interrupt or reset

■ Flexible Reset Sources

   – Power-on reset (POR)

   – Reset pin assertion

   – Brown-out (BOR) detector alerts to system power drops

   – Software reset

   – Watchdog timer reset

   – Internal low drop-out (LDO) regulator output goes unregulated

■ Additional Features

   – Six reset sources

   – Programmable clock source control

   – Clock gating to individual peripherals for power savings

   – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller

   – Debug access via JTAG and Serial Wire interfaces

   – Full JTAG boundary scan

■ Industrial-range 48-pin RoHS-compliant LQFP package

Target Applications

■ Factory automation and control

■ Industrial control power devices

■ Building and home automation

■ Stepper motors

■ Brushless DC motors

■ AC induction motors