Description
. HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V . LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C . HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH = tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS175 The M54/74HC175is ahigh speedCMOSQUADDTYPE FLIP-FLOP WITH CLEAR fabricated in silicon gate CMOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These four flip-flops are controlled by a clock input (CLOCK) and a clear input (CLEAR). The information data applied to the D inputs (1D to4D) are transfered to the outputs (1Q to 4Q and 1Q to 4Q) on the positive-going edge of the clock pulse. The reset function is accomplished when the clear input is taken low and all Q outputs are kept low regardless of other input conditions. All inputs are equipped with protection circuits against static discharge and transient excess voltage. 1/11