• Two 1:4, low skew, low additive jitter LVPECL output pairs
• Two differential clock input pairs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• Output skew: 8ps (typical)
• Propagation delay: 270ps (maximum)
• Low additive phase jitter, RMS: 47fs (maximum)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 93mA (maximum)
• Available in lead-free (RoHS 6), 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Supports case temperature  105°C operations
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).