General description
The 74HC594; 74HCT594 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register. Separate clock and reset inputs are provided on both shift and storage
registers. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading. Data is shifted on the LOW-to-HIGH transitions of the SHCP input, and the
data in the shift register is transferred to the storage register on a LOW-to-HIGH transition
of the STCP input. If both clocks are connected together, the shift register will always be
one clock pulse ahead of the storage register. A LOW level on one of the two register
reset pins (SHR and STR) will clear the corresponding register. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
Features and benefits
 Synchronous serial input and output
 Complies with JEDEC standard No.7A
 8-bit parallel output
 Shift and storage registers have independent direct clear and clocks
 Independent clocks for shift and storage registers
 100 MHz (typical)
 Input levels:
 For 74HC594: CMOS level
 For 74HCT594: TTL level
 Multiple package options
 Specified from 40 C to +85 C and from 40 C to +125 C

Applications
 Serial-to parallel data conversion
 Remote control holding register