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74HC4052DB 数据表 (PDF) - Nexperia B.V. All rights reserved

74HC4052DB Datasheet PDF - Nexperia B.V. All rights reserved
部件名 74HC4052DB
下载  74HC4052DB 下载
文件大小   891.6 Kbytes
页   27 Pages
制造商  NEXPERIA [Nexperia B.V. All rights reserved]
网页  https://www.nexperia.com/
标志 NEXPERIA - Nexperia B.V. All rights reserved
功能描述 Dual 4-channel analog multiplexer/demultiplexer

74HC4052DB Datasheet (PDF)

Go To PDF Page 下载 数据表
74HC4052DB Datasheet PDF - Nexperia B.V. All rights reserved

部件名 74HC4052DB
下载  74HC4052DB Click to download

文件大小   891.6 Kbytes
页   27 Pages
制造商  NEXPERIA [Nexperia B.V. All rights reserved]
网页  https://www.nexperia.com/
标志 NEXPERIA - Nexperia B.V. All rights reserved
功能描述 Dual 4-channel analog multiplexer/demultiplexer

74HC4052DB 数据表 (HTML) - Nexperia B.V. All rights reserved


74HC4052DB 产品详情

General description
The 74HC4052; 74HCT4052 is a dual single-pole quad-throw analog switch (2x SP4T)
suitable for use in analog or digital 4:1 multiplexer/demultiplexer applications. Each switch
features four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common
input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are
common to both switches. When E is HIGH, the switches are turned off. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
Features and benefits
 Wide analog input voltage range from 5 V to +5 V
 Low ON resistance:
 80  (typical) at VCC  VEE = 4.5 V
 70  (typical) at VCC  VEE = 6.0 V
 60  (typical) at VCC  VEE = 9.0 V
 Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
 Typical ‘break before make’ built-in
 Complies with JEDEC standard no. 7A
 Input levels:
 For 74HC4052: CMOS level
 For 74HCT4052: TTL level
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Specified from 40 C to +85 C and 40 C to +125 C
Applications
 Analog multiplexing and demultiplexing
 Digital multiplexing and demultiplexing
 Signal gating




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