General description
The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
Features and benefits
 5 V tolerant inputs/outputs for interfacing with 5 V logic
 Wide supply voltage range from 1.2 V to 3.6 V
 CMOS low-power consumption
 Direct interface with TTL levels
 Balanced propagation delays
 All inputs have Schmitt-trigger action
 Complies with JEDEC standard JESD8-B/JESD36
 ESD protection:
 HBM JESD22-A114-D exceeds 2000 V
 CDM JESD22-C101-C exceeds 1000 V
 Specified from 40 C to +85 C and 40 C to +125 C.
Applications
 Serial-to-parallel data conversion
 Remote control holding register