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74LVC8T245BZX 数据表 (PDF) - Nexperia B.V. All rights reserved

74LVC8T245BZX Datasheet PDF - Nexperia B.V. All rights reserved
部件名 74LVC8T245BZX
下载  74LVC8T245BZX 下载
文件大小   382.83 Kbytes
页   28 Pages
制造商  NEXPERIA [Nexperia B.V. All rights reserved]
网页  https://www.nexperia.com/
标志 NEXPERIA - Nexperia B.V. All rights reserved
功能描述 8-bit dual supply translating transceiver; 3-state

74LVC8T245BZX Datasheet (PDF)

Go To PDF Page 下载 数据表
74LVC8T245BZX Datasheet PDF - Nexperia B.V. All rights reserved

部件名 74LVC8T245BZX
下载  74LVC8T245BZX Click to download

文件大小   382.83 Kbytes
页   28 Pages
制造商  NEXPERIA [Nexperia B.V. All rights reserved]
网页  https://www.nexperia.com/
标志 NEXPERIA - Nexperia B.V. All rights reserved
功能描述 8-bit dual supply translating transceiver; 3-state

74LVC8T245BZX 数据表 (HTML) - Nexperia B.V. All rights reserved


74LVC8T245BZX 产品详情

General description
The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs
that enable bidirectional level translation. They feature two data input-output ports (pins An and
Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and
VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making
the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V,
3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to
VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission
from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are
effectively isolated.
The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and
B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic
level.
Features and benefits
• Wide supply voltage range:
• VCC(A): 1.2 V to 5.5 V
• VCC(B): 1.2 V to 5.5 V
• High noise immunity
• Complies with JEDEC standards:
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM JESD22-A114F Class 3A exceeds 4000 V
• MM JESD22-A115-B exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Maximum data rates:
• 420 Mbps (3.3 V to 5.0 V translation)
• 210 Mbps (translate to 3.3 V)
• 140 Mbps (translate to 2.5 V)
• 75 Mbps (translate to 1.8 V)
• 60 Mbps (translate to 1.5 V)
• Suspend mode
• Latch-up performance exceeds 100 mA per JESD 78B Class II
• ±24 mA output drive (VCC = 3.0 V)
• Inputs accept voltages up to 5.5 V
• Low power consumption: 30 μA maximum ICC
• IOFF circuitry provides partial Power-down mode operation
• Specified from -40 °C to +85 °C and -40 °C to +125 °C




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