INTRODUCTION
The ST10F163 is a Flash derivative of the STMicroelectronics ST10 family of 16-bit microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. 128KBytes of an electrically erasable and re-programmable Flash EPROM is provided on-chip.

■ HIGH PERFORMANCE CPU
    – HIGH PERFORMANCE 16-BIT CPU WITH 4-STAGE PIPELINE
    – 80ns INSTRUCTION CYCLE TIME @ 25MHz CPU CLOCK
    – 400ns MULTIPLICATION (16 × 16 BITS)
    – 800ns DIVISION (32 / 16 BIT)
    – ENHANCED BOOLEAN BIT MANIPULATION FACILITIES
    – ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS
    – SINGLE-CYCLE CONTEXT SWITCHING SUPPORT
■ MEMORY ORGANIZATION
    – UP TO 16 MBYTES LINEAR ADDRESS SPACE FOR CODE AND DATA (1MBYTE WITH SSP USED)
    – 1 KBYTES ON-CHIP RAM
    – 128 KBYTES ON-CHIP FLASH MEMORY
    – 4 INDEPENDENTLY ERASABLE BANKS OF FLASH
■ FAST AND FLEXIBLE BUS
    – PROGRAMMABLE EBC
    – 8-BIT OR 16-BIT EXTERNAL DATA BUS
    – MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRESS/DATA BUSES
    – FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
    – HOLD AND HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT
■ ON-CHIP BOOTSTRAP LOADER
■ FAIL-SAFE PROTECTION
    – PROGRAMMABLE WATCHDOG TIMER
    – OSCILLATOR WATCHDOG
■ INTERRUPT
    – 8-CHANNEL INTERRUPT-DRIVEN SINGLE-CYCLE DATA TRANSFER FACILITIES VIA PERIPHERAL EVENT CONTROLLER (PEC)
    – 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 20 SOURCES, SAMPLE-RATE DOWN TO 40ns
■ TIMERS
    – TWO GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS
■ CLOCK GENERATION
    – ON-CHIP PLL
    – DIRECT OR PRESCALED CLOCK INPUT
■ UP TO 77 GENERAL PURPOSE I/O LINES
■ IDLE AND POWER DOWN MODES
■ SERIAL CHANNELS
    – SYNCHRONOUS/ASYNCHRONOUS
    – HIGH-SPEEDSYNCHRONOUS SERIALPORTSSP
■ DEVELOPMENT SUPPORT
    – C-COMPILERS, MACRO-ASSEMBLER PACKAGES, EMULATORS, EVALUATION BOARDS, HLL-DEBUGGERS, SIMULATORS, LOGIC ANALYZER DISASSEMBLERS, PROGRAMMING BOARDS
■ PACKAGE
    – 100-PIN THIN QUAD FLAT PACK (TQFP)