Description
The V54C333322V is a 33,554,432 bits synchronous high data rate DRAM organized as 2 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.

Features
■ JEDEC Standard 3.3V Power Supply
■ The V54C333322V is ideally suited for high  performance graphics peripheral applications
■ Single Pulsed RAS Interface
■ Programmable CAS Latency: 2, 3
■ All Inputs are sampled at the positive going edge  of clock
■ Programmable Wrap Sequence: Sequential or  Interleave
■ Programmable Burst Length: 1, 2, 4, 8 and Full  Page for Sequential and 1, 2, 4, 8 for Interleave
■ DQM 0-3 for Byte Masking
■ Auto & Self Refresh
■ 2K Refresh Cycles/32 ms
■ Burst Read with Single Write Operation