Description
The V61C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Features
■ High-speed: 10, 12, 15 ns
■ Low Power Dissipation:
   – CMOS Standby: 0.5 mA (Max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 2V)
■ Single 5V ± 10% Power Supply
■ Packages
   – 28-pin TSOP (Standard)
   – 28-pin 300 mil SOJ