Dual 4-line-to-1-line Data Selectors / Multiplexers (with three-state outputs)

This data selector / multiplexer contains inverters and drivers to supply fully complementary, on-ship, binary decoding data selection to AND-OR gates.
Separate output control inputs are provided for each of the two four-line sections. The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at high-impedance state) the low-impedance of the single enabled output will drive the bus line to a high or low logic level.