FEATURES ♦ Memory configuration OTP ROM size: 2K * 16 bits. RAM size: 64 * 8 bits. Four levels stack buffer ♦ I/O pin configuration Bi-directional: P0, P1, P5. Input only: P1.5. Programmable open-drain: P1.0. Wakeup: P0, P1 level change trigger Pull-up resisters: P0, P1, P5. External Interrupt trigger edge: P0.0 controlled by PEDGE register. P0.1 is falling edge trigger only. ♦ 3-Level LVD. Reset system and power monitor. ♦ Four interrupt sources Two internal interrupts: T0, TC0. One external interrupts: INT0, INT1. ♦ Powerful instructions One clocks per instruction cycle (1T) Most of instructions are one cycle only. All ROM area JMP instruction. All ROM area CALL address instruction. All ROM area lookup table function (MOVC) ♦ Two 8-bit Timer/Counter T0: Basic timer TC0: Auto-reload timer/Counter/PWM0/Buzzer output ♦ On chip watchdog timer and clock source is internal low clock RC type (16KHz @3V, 32KHz @5V). ♦ Dual system clocks External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal high clock: 16MHz RC type. Internal low clock: RC type 16KHz(3V), 32KHz(5V) ♦ Operating modes Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Green mode: Periodical wakeup by T0 Timer ♦ Package (Chip form support) PDIP 20 pins PDIP 18 pins PDIP 14 pins SOP 20 pins SOP 18 pins SOP 14 pins SSOP 20 pins
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