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PEX8114 数据表 (PDF) - PLX Technology

PEX8114 Datasheet PDF - PLX Technology
部件名 PEX8114
下载  PEX8114 下载

文件大小   1362.21 Kbytes
  4 Pages
制造商  PLX [PLX Technology]
网页  http://www.plxtech.com
标志 PLX - PLX Technology
功能描述 PCI Express-to-PCI/PCI-X Bridge

PEX8114 Datasheet (PDF)

Go To PDF Page 下载 数据表
PEX8114 Datasheet PDF - PLX Technology

部件名 PEX8114
下载  PEX8114 Click to download

文件大小   1362.21 Kbytes
  4 Pages
制造商  PLX [PLX Technology]
网页  http://www.plxtech.com
标志 PLX - PLX Technology
功能描述 PCI Express-to-PCI/PCI-X Bridge

PEX8114 数据表 (HTML) - PLX Technology

PEX8114 Datasheet HTML 1Page - PLX Technology PEX8114 Datasheet HTML 2Page - PLX Technology PEX8114 Datasheet HTML 3Page - PLX Technology PEX8114 Datasheet HTML 4Page - PLX Technology

PEX8114 产品详情

Flexible, High-Performance Bridge in a Small Package

The PLX Technology ExpressLane™ PEX 8114 is a high performance bridge that enables designers to migrate legacy PCI and PCI-X bus interfaces to the new advanced serial PCI Express™ interface. This flexible device supports forward and reverse transparent bridging.

The bridge is equipped with a standard, but flexible PCI Express port that scales to x1, x2 or x4 lanes with a maximum of 1 Gigabyte per second of throughput per transmit and receive direction. With four 2.5 Gbps integrated SerDes, the standard PCI Express signaling delivers the highest bandwidth with the lowest possible pin count using LVDS technology.



Features

General Features

o Forward and Reverse bridging

o Reverse bridging root functions

o Transparent bridging

o Standard 256 Plastic BGA package (17mm x 17mm)

o Leaded and lead-free ROHS versions available

o Low power – 2W

o No heat sink required

o EEPROM configuration option

o 1.0 V core supply voltage

o DC and AC JTAG (1149.1 and 1149.6)

Scalable PCI Express Interface

o x4 Link (configurable as x1, x2 or x4)

o Full-duplex PCI Express lanes; 2.5 Gbps each

o Automatic lane reversal

o 8b/10b encoding

o Link training (auto-negotiate to smallest link width)

o 256 byte maximum payload size

o PCI Express Base specification 1.0a compliant

o End-to-end CRC and data poisoning

o Advanced error reporting

o Link and device power management

o Advanced flow control

o Hot Plug

o Turn off unused lanes for power reduction

Advanced PCI-X Interface

o PCI-X (v 1.0b): 64 bits at 133, 100 or 66 MHz

o PCI 3.0: 32 or 64 bits at 66, 50, 33 or 25 MHz

o 8-outstanding split transactions

o Internal arbiter supports up to 4 external masters

o 3.3V I/O

o Message Signal Interrupt (MSI) support

o Provides up to four PCI/PCI-X clocks

o Scratchpad and doorbell registers




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