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DM9801E 数据表 (PDF) - Davicom Semiconductor, Inc.

DM9801E Datasheet PDF - Davicom Semiconductor, Inc.
部件名 DM9801E
下载  DM9801E 下载

文件大小   35.03 Kbytes
  2 Pages
制造商  DAVICOM [Davicom Semiconductor, Inc.]
网页  http://www.davicom.com.tw
标志 DAVICOM - Davicom Semiconductor, Inc.
功能描述 1M Home Phoneline Network Physical Layer Single Chip Transceiver

DM9801E Datasheet (PDF)

Go To PDF Page 下载 数据表
DM9801E Datasheet PDF - Davicom Semiconductor, Inc.

部件名 DM9801E
下载  DM9801E Click to download

文件大小   35.03 Kbytes
  2 Pages
制造商  DAVICOM [Davicom Semiconductor, Inc.]
网页  http://www.davicom.com.tw
标志 DAVICOM - Davicom Semiconductor, Inc.
功能描述 1M Home Phoneline Network Physical Layer Single Chip Transceiver

DM9801E 数据表 (HTML) - Davicom Semiconductor, Inc.

DM9801E Datasheet HTML 1Page - Davicom Semiconductor, Inc. DM9801E Datasheet HTML 2Page - Davicom Semiconductor, Inc.

DM9801E 产品详情

General Description

The DM9801 is a physical-layer, single-chip, low-power transceiver for 1M Home Phoneline Network applications. On the media side, it provides an interface to a Home Phoneline wiring system. The reconciliation layer interfaces to the DM9801 either through an IEEE802.3u subset Media Independent Interface (MII) or a pseudo-standard General Purpose Serial Interface (GPSI). A management interface is provided by MDIO/MDC when operating in MII mode, or a Serial Peripheral Interface bus when operating in GPSI mode.



Features

• 1M Home Phoneline Network physical-layer, single chip transceiver

• Supports the MII including the MDIO/MDC serial management interface

• Supports the GPSI including a SPI serial management interface

• Supports Link Integrity function

• Smart equalizer circuit for 1M receiver

• Supports Patent Pending 4-wire operation

• Supports hardware or software speed select

• Supports Interrupt on change, eliminates management polling

• Flexible built-in LED support for TX Activity, RX Activity and Collision Indication or Activity, Link state and Collision

• Digital PLL circuit using advanced digital algorithm to reduce jitter

• Low-power, high-performance CMOS process

• Available in a small outline 100-pin LQFP

• 3.3V DC power with 5V DC tolerant I/O




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