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PC100 数据表 (PDF) - Samsung semiconductor

PC100 Datasheet PDF - Samsung semiconductor
部件名 PC100
下载  PC100 下载

文件大小   151.64 Kbytes
  10 Pages
制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor
功能描述 PC100 SDRAM MODULE Preliminary

PC100 Datasheet (PDF)

Go To PDF Page 下载 数据表
PC100 Datasheet PDF - Samsung semiconductor

部件名 PC100
下载  PC100 Click to download

文件大小   151.64 Kbytes
  10 Pages
制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
标志 SAMSUNG - Samsung semiconductor
功能描述 PC100 SDRAM MODULE Preliminary

PC100 数据表 (HTML) - Samsung semiconductor

PC100 Datasheet HTML 1Page - Samsung semiconductor PC100 Datasheet HTML 2Page - Samsung semiconductor PC100 Datasheet HTML 3Page - Samsung semiconductor PC100 Datasheet HTML 4Page - Samsung semiconductor PC100 Datasheet HTML 5Page - Samsung semiconductor PC100 Datasheet HTML 6Page - Samsung semiconductor PC100 Datasheet HTML 7Page - Samsung semiconductor PC100 Datasheet HTML 8Page - Samsung semiconductor PC100 Datasheet HTML 9Page - Samsung semiconductor PC100 Datasheet HTML 10Page - Samsung semiconductor

PC100 产品详情

GENERAL DESCRIPTION
The Samsung KMM366S1623CT is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S1623CT consists of sixteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM.
The KMM366S1623CT is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURE
• Performance range
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
   Latency (Access from column address)
   Burst length (1, 2, 4, 8 & Full page)
   Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
   system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component




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