FUNCTIONAL DESCRIPTION
The LH543620 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can replace four or more nine-bit-wide FIFOs in many applications.

FEATURES
• Fast Cycle Times: 20/25/30 ns
• Selectable 36/18/9-Bit Word Width for Both Input Port and Output Port
• Byte-Order-Reversal Function (i.e., ‘Big-Endian’ ↔ ‘Little-Endian’ Conversion)
• 16-mA-IOL Three-State Outputs
• Automatic Byte Parity Checking
• Selectable Byte Parity Generation
• Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty
• All FIFO Status Flags are Synchronous (AE, HF, AF Through Programming of Control Register)
• Programmed Values may be entered from either Port
• Two Enable Control Signals for each Port
• Mailbox Register with Synchronized Flags
• Asynchronous Data-Bypass Function
• ‘Smart’ Data-Retransmit Function
• Configurable for Paralleled FIFO Operation (72-Bit Data Width)
• Space-Saving PQFP and TQFP 1 Packages
• PQFP-to-PGA Package Conversion 2