General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features.

Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

High Capacity
• 15K to 1 Million System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os

Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance

In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO® devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® Designed to Secure FPGA Contents

High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†, and LVCMOS 2.5 V / 5.0 V Input†
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above)
• Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)†

ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available with or without Debug