Introduction
The AMD-K6 processor implements advanced design techniques known as the RISC86 microarchitecture. The RISC86 microarchitecture is a decoupled decode/execution design approach that yields superior sixth-generation performance for x86-based software. This chapter describes the techniques used and the functional elements of the RISC86 microarchitecture.

AMD-K6® Processor
■ Advanced 6-Issue RISC86® Superscalar Microarchitecture
   ◆ Seven parallel specialized execution units
   ◆ Multiple sophisticated x86-to-RISC86 instruction decoders
   ◆ Advanced two-level branch prediction
   ◆ Speculative execution
   ◆ Out-of-order execution
   ◆ Register renaming and data forwarding
   ◆ Issues up to six RISC86 instructions per clock
■ Large On-Chip Split 64-Kbyte Level-One (L1) Cache
   ◆ 32-Kbyte instruction cache with additional predecode cache
   ◆ 32-Kbyte writeback dual-ported data cache
   ◆ MESI protocol support
■ High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit
■ High-Performance Industry-Standard MMX™ Instructions
■ 321-Pin Ceramic Pin Grid Array (CPGA) Package (Socket 7 Compatible)
■ Industry-Standard System Management Mode (SMM)
■ IEEE 1149.1 Boundary Scan
■ Full x86 Binary Software Compatibility