32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

• Socket and Object Code Compatible with 80960CA
• Two Instructions/Clock Sustained Execution
• Four 59 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-bit Burst Bus with Pipelining

■ 32-bit Parallel Architecture
   — Two Instructions/clock Execution
   — Load/Store Architecture
   — Sixteen 32-bit Global Registers
   — Sixteen 32-bit Local Registers
   — Manipulate 64-bit Bit Fields
   — 11 Addressing Modes
   — Full Parallel Fault Model
   — Supervisor Protection Model
■ Fast Procedure Call/Return Model
   — Full Procedure Call in 4 clocks
■ On-Chip Register Cache
   — Caches Registers on Call/Ret
   — Minimum of 6 Frames provided
   — Up to 15 Programmable Frames
■ On-Chip Instruction Cache
   — 4 Kbyte Two-Way Set Associative
   — 128-bit Path to Instruction Sequencer
   — Cache-Lock Modes
   — Cache-Off Mode
■ On-Chip Data Cache
   — 1 Kbyte Direct-Mapped, Write Through
   — 128 bits per Clock Access on Cache Hit
■ Product Grades Available
   — SE3: -40°C to +110°C
■ High Bandwidth On-Chip Data RAM
   — 1 Kbytes On-Chip RAM for Data
   — Sustain 128 bits per clock access
■ Four On-Chip DMA Channels
   — 59 Mbytes/s Fly-by Transfers
   — 32 Mbytes/s Two-Cycle Transfers
   — Data Chaining
   — Data Packing/Unpacking
   — Programmable Priority Method
■ 32-Bit Demultiplexed Burst Bus
   — 128-bit Internal Data Paths to and from Registers
   — Burst Bus for DRAM Interfacing
   — Address Pipelining Option
   — Fully Programmable Wait States
   — Supports 8, 16 or 32-bit Bus Widths
   — Supports Unaligned Accesses
   — Supervisor Protection Pin
■ Selectable Big or Little Endian Byte Ordering
■ High-Speed Interrupt Controller
   — Up to 248 External Interrupts
   — 32 Fully Programmable Priorities
   — Multi-mode 8-bit Interrupt Port
   — Four Internal DMA Interrupts
   — Separate, Non-maskable Interrupt Pin
   — Context Switch in 750 ns Typical