Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a new column address.

Features
• PC100/133 compliant
• Organization
    - 2,097,152 words × 8 bits × 4 banks (8M×8)
    - 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous
    - All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/BA1 (bank select)
• High speed
    - 133/125/100 MHz
    - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
• Low power consumption
    - Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
    - 400 mil, 54-pin TSOP II
• Read/write data masking
• Programmable burst length (1/2/4/8/full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (2/3)