Features
• Dedicated clock buffer power pins for reduced noise,
   crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of five clocks
• One REF XIN clock output
• SMBus clock control interface for individual clock
   disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
   interference (EMI)
• OE pin for entire output bank enable control and
   testability
• 28-pin SSOP and TSSOP packages