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CY7C68000-56PVC 数据表 (PDF) - Cypress Semiconductor

CY7C68000-56PVC Datasheet PDF - Cypress Semiconductor
部件名 CY7C68000-56PVC
下载  CY7C68000-56PVC 下载
文件大小   237.06 Kbytes
  14 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 TX2 USB 2.0 UTMI Transceiver

CY7C68000-56PVC Datasheet (PDF)

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CY7C68000-56PVC Datasheet PDF - Cypress Semiconductor

部件名 CY7C68000-56PVC
下载  CY7C68000-56PVC Click to download

文件大小   237.06 Kbytes
  14 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 TX2 USB 2.0 UTMI Transceiver

CY7C68000-56PVC 数据表 (HTML) - Cypress Semiconductor


CY7C68000-56PVC 产品详情

EZ-USB TX2™ Features
The Cypress EZ-USB TX2™ is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial/deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The TX2 provides a high-speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth. This allows the system designer to keep the complex high speed analog USB components external to the digital ASIC which decreases development time and associated risk. A standard interface is provided that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/01. Two packages are defined for the family: 56-pin SSOP and 56-pin QFN.

The function block diagram is shown in Figure 1-1. The features of the EX-USB TX2 are:
• UTMI-compliant/USB-2.0-certified for device operation
• Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second
• Serial-to-parallel and parallel-to-serial conversions
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface
• Synchronous field and EOP detection on receive packets
• Synchronous field and EOP generation on transmit packets
• Data and clock recovery from the USB serial stream
• Bit stuffing/unstuffing; bit stuff error detection
• Staging register to manage data rate variation due to bit stuffing/unstuffing
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
• Ability to switch between FS and HS terminations and signaling
• Supports detection of USB reset, suspend, and resume
• Supports HS identification and detection as defined by the USB 2.0 Specification
• Supports transmission of resume signaling
• 3.3 V operation
• Two package options—56-pin QFN, and 56-pin SSOP
• All required terminations, including 1.5K-ohm pull up on DPLUS, are internal to the chip
• Supports USB 2.0 test modes

Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking




类似零件编号 - CY7C68000-56PVC

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关于 Cypress Semiconductor


赛普拉斯半导体是一家美国公司,专门从事高性能数字和模拟集成电路(ICS)的设计和制造。
该公司成立于1982年,总部位于美国加利福尼亚州圣何塞。
赛普拉斯(Cypress)提供了广泛的产品,包括微控制器,内存产品,无线连接解决方​​案以及其他数字和模拟IC。
该公司的产品用于各种应用,例如消费电子,汽车系统,工业系统等。
赛普拉斯以其在嵌入式系统领域的混合信号和可编程系统,高质量产品和创新方面的专业知识而闻名。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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