Introduction
The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device.

Features
• Jitter peak-peak (TYPICAL) = 35 ps
• LVPECL output
• Default Select option
• Serially-configurable multiply ratios
• Output edge-rate control
• 16-pin TSSOP
• High frequency
• 3.3V operation

Benefits
   High-accuracy clock generation
   One pair of differential output drivers
   Phase-locked loop (PLL) multiplier select
   Eight-bit feedback counter and six-bit reference counter for high accuracy
   Minimize electromagnetic interference (EMI)
   Industry-standard, low-cost package saves on board space
   125- to 400-MHz (-1) or to 500-MHz (-2) extended output range for high-speed applications
   Enables application compatibility