2

ICS950410

Advance Information

0888—04/06/04

Pin Descriptions

PIN # PIN NAME

PIN

TYPE

DESCRIPTION

1

~*FS0/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

2

VDDHTT

PWR

Supply for HTT clocks, nominal 3.3V.

3

X1

IN

Crystal input, Nominally 14.318MHz.

4

X2

OUT

Crystal output, Nominally 14.318MHz

5

GND

PWR

Ground pin.

6

*ModeA/HTTCLK0

I/O

Mode selection latch input pin / Hyper Transport output.

7

*ModeB/PCICLK8/HTTCLK1

I/O

Mode selection latch input pin / PCI clock output / Hyper Transport output.

8

PCICLK9/HTTCLK2

OUT

PCI clock output / Hyper Transport output.

9

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

10

GND

PWR

Ground pin.

11

PCICLK11/HTTCLK3

OUT

PCI clock output / Hyper Transport output.

12

*FS2/PCICLK10

I/O

Frequency select latch input pin / 3.3V PCI clock output.

13

PCICLK0

OUT

PCI clock output.

14

PCICLK1

OUT

PCI clock output.

15

GND

PWR

Ground pin.

16

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

17

PCICLK2

OUT

PCI clock output.

18

PCICLK3

OUT

PCI clock output.

19

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

20

GND

PWR

Ground pin.

21

2XPCICLK4

OUT

PCI clock output. This output is default @ 2X drive and can be programmed to lower

drive via IIC.

22

2XPCICLK5

OUT

PCI clock output. This output is default @ 2X drive and can be programmed to lower

drive via IIC.

23

2XPCICLK6

OUT

PCI clock output. This output is default @ 2X drive and can be programmed to lower

drive via IIC.

24

2XPCICLK7

OUT

PCI clock output. This output is default @ 2X drive and can be programmed to lower

drive via IIC.

25

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

26

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

27

24_48MHz/Sel24_48#*

I/O

24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =

24MHz.

28

AVDD48

PWR

Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V

29

GND

PWR

Ground pin.

30

48MHz/FS3**

I/O

Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin

31

PD#*

IN

Asynchronous active low input pin used to power down the device. The internal

clocks are disabled and the VCO and the crystal are stopped.

32

Turbo#

IN

Real time input pin to change frequency to a pre-programmed under or over clock

entries located in IIC Rom table.

33

GND

PWR

Ground pin.

34

CPUCLK8C2

OUT

Complimentary clock of differential 3.3V push-pull K8 pair.

35

CPUCLK8T2

OUT

True clock of differential 3.3V push-pull K8 pair.

36

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

37

GND

PWR

Ground pin.

38

CPUCLK8C1

OUT

Complimentary clock of differential 3.3V push-pull K8 pair.

39

CPUCLK8T1

OUT

True clock of differential 3.3V push-pull K8 pair.

40

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

41

CPUCLK8C0

OUT

Complimentary clock of differential 3.3V push-pull K8 pair.

42

CPUCLK8T0

OUT

True clock of differential 3.3V push-pull K8 pair.

43

GND

PWR

Ground pin.

44

VDDA

PWR

3.3V power for the PLL core.

45

Reset#

OUT

Real time system reset signal for frequency gear ratio change or watchdog timer

timeout. This signal is active low.

46

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

47

GND

PWR

Ground pin.

48

REF1/FS1*

I/O

14.318 MHz reference clock / Frequency select latch input pin.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength