AD9243EB datasheet(20/25 Pages) AD

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AD9243

REV. A

–19–

GROUNDING AND DECOUPLING

Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recom-

mended to provide optimal grounding and power schemes. The

use of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power

plane, PCB insulation, and ground plane.

These characteristics result in both a reduction of electro-

magnetic interference (EMI) and an overall improvement in

performance.

It is important to design a layout that prevents noise from coupling

onto the input signal. Digital signals should not be run in paral-

lel with input signal traces and should be routed away from the

input circuitry. While the AD9243 features separate analog and

digital ground pins, it should be treated as an analog compo-

nent. The AVSS, DVSS and DRVSS pins must be joined together

directly under the AD9243. A solid ground plane under the A/D is

acceptable if the power and ground return currents are managed

carefully. Alternatively, the ground plane under the A/D may

contain serrations to steer currents in predictable directions

where cross-coupling between analog and digital would other-

wise be unavoidable. The AD9243/EB ground layout, shown in

Figure 54, depicts the serrated type of arrangement. The analog

and digital grounds are connected by a jumper below the A/D.

Analog and Digital Supply Decoupling

The AD9243 features separate analog and digital supply and

ground pins, helping to minimize digital corruption of sensitive

analog signals.

FREQUENCY – kHz

120

100

1000

100

AVDD

DVDD

Figure 45. AD9243 PSSR vs. Frequency

Figure 45 shows the power supply rejection ratio vs. frequency

for a 200 mV p-p ripple applied to both AVDD and DVDD.

In general, AVDD, the analog supply, should be decoupled to

AVSS, the analog common, as close to the chip as physically

possible. Figure 46 shows the recommended decoupling for the

analog supplies; 0.1

µF ceramic chip capacitors should provide

adequately low impedance over a wide frequency range. Note

that the AVDD and AVSS pins are co-located on the AD9243

to simplify the layout of the decoupling capacitors and provide

the shortest possible PCB trace lengths. The AD9243/EB power

plane layout, shown in Figure 55 depicts a typical arrangement

using a multilayer PCB.

0.1 F

AVDD

AVSS

AD9243

0.1 F

AVDD

AVSS

Figure 46. Analog Supply Decoupling

The CML is an internal analog bias point used internally by the

AD9243. This pin must be decoupled with at least a 0.1

µF

capacitor as shown in Figure 47. The dc level of CML is ap-

proximately AVDD/2. This voltage should be buffered if it is to

be used for any external biasing.

0.1 F

CML

AD9243

Figure 47. CML Decoupling

The digital activity on the AD9243 chip falls into two general

categories: correction logic, and output drivers. The internal

correction logic draws relatively small surges of current, mainly

during the clock transitions. The output drivers draw large

current impulses while the output bits are changing. The size

and duration of these currents are a function of the load on the

output bits: large capacitive loads are to be avoided. Note that

the internal correction logic of the AD9243 is referenced DVDD

while the output drivers are referenced to DRVDD.

The decoupling shown in Figure 48, a 0.1

µF ceramic chip

capacitor, is appropriate for a reasonable capacitive load on the

digital outputs (typically 20 pF on each pin). Applications

involving greater digital loads should consider increasing the

digital decoupling proportionally, and/or using external buffers/

latches.

0.1 F

DVDD

DVSS

AD9243

DRVDD

DRVSS

0.1 F

Figure 48. Digital Supply Decoupling

A complete decoupling scheme will also include large tantalum

or electrolytic capacitors on the PCB to reduce low-frequency

ripple to negligible levels. Refer to the AD9243/EB schematic

and layouts in Figures 51–55 for more information regarding the

placement of decoupling capacitors.

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