1/11

April 2001

s

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS

s

50

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74ACT573 is an advanced high-speed CMOS

OCTAL D-TYPE LATCH with 3 STATE OUTPUT

NON INVERTING fabricated with sub-micron

technology.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input .

When the LE is taken low, the Q outputs will be

latched precisely or inversely at the logic level of D

input data. While the

(OE) input is low, the 8

outputs will be in a normal logic state (high or low

logic level) and while high level the outputs will be

in a high impedance state.

This device is designed to interface directly High

Speed CMOS systems with TTL and NMOS

components.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74ACT573

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUTS (NON INVERTED)

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

74ACT573B

SOP

74ACT573M

74ACT573MTR

TSSOP

74ACT573TTR

TSSOP

DIP

SOP