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AT89C5131A-RDTIM 数据表(PDF) 113 Page - ATMEL Corporation |
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AT89C5131A-RDTIM 数据表(HTML) 113 Page - ATMEL Corporation |
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113 / 184 page  113 AT89C5130A/31A-M 4337C–USB–02/05 Figure 52. Format and State in the Slave Transmitter Mode SSLA R A Data A Data P or S A A8h B8h C0h P or S A C8h All 1’s A B0h Data A n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus Reception of the own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (AA=0) Table 86. Status in Slave Transmitter Mode Status Code (SSCS) Status of the 2-wire bus and 2-wire hardware Application Software Response Next Action Taken By 2-wire Software To/from SSDAT To SSCON STA STO SI AA A8h Own SLA+R has been received; ACK has been returned Load data byte or Load data byte X X 0 0 0 0 0 1 Last data byte will be transmitted and NOT ACK will be received Data byte will be transmitted and ACK will be received B0h Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned Load data byte or Load data byte X X 0 0 0 0 0 1 Last data byte will be transmitted and NOT ACK will be received Data byte will be transmitted and ACK will be received B8h Data byte in SSDAT has been transmitted; NOT ACK has been received Load data byte or Load data byte X X 0 0 0 0 0 1 Last data byte will be transmitted and NOT ACK will be received Data byte will be transmitted and ACK will be received |
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