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AT89C5131A-RDTIM 数据表(PDF) 26 Page - ATMEL Corporation |
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AT89C5131A-RDTIM 数据表(HTML) 26 Page - ATMEL Corporation |
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26 / 184 page  26 AT89C5130A/31A-M 4337C–USB–02/05 Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 34) that allows the program code to switch between them (see Figure 10). Figure 10. Use of Dual Pointer Table 34. AUXR1 Register AUXR1- Auxiliary Register 1(0A2h) Reset Value = XX[BLJB]X X0X0b Not bit addressable a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. External Data Memory AUXR1(A2H) DPS DPH(83H) DPL(82H) 0 7 DPTR0 DPTR1 765 43210 - - ENBOOT - GF3 0 - DPS Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5 ENBOOT Enable Boot Flash Cleared to disable boot ROM. Set to map the boot ROM between F800h - 0FFFFh. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3 GF3 This bit is a general-purpose user flag. 2 0 Always cleared. 1- Reserved The value read from this bit is indeterminate. Do not set this bit. 0DPS Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. |
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