5

ATSAM2193/ATSAM2193-G

2695A–DRMSD–06/03

Figure 2. Pinout by Pin Coordinate - 44-ball TFBGA (Top View)

CKOUT

C6

OUT

Buffered X2 output, can be used to drive external DAC master clock (256 * Fs)

LFT

G7

-

PLL external RC network.

RESET

E7

IN

Reset input, active low. This is a Schmitt trigger input, allowing direct connection to an RC

network.

PWROUT

E1

PWR

Power switch output. Use this pin to supply 2.5V nominal core voltage by connecting it to all

V

PDWN

F3

IN

Power down, active low. When power down is active, all outputs are set to logic level 0. The

PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply

is removed from the core. To exit from power down, PDWN must be set to V

applied. When unused this pin must be connected to V

TEST0 -

TEST1

B7, B2

IN

Test pins, should be grounded.

RUN

A3

OUT

When high, indicates synthesizer is up and running.

Table 3. Pin by Function - 44-ball TFBGA Package (Continued)

Pin Name

Pin Number

Type

Function

WSBD

D5

RUN

GND

D3

DACSEL VC3

D6

TEST1

D4

GND MIDI IN

D2

TEST0

D7

DABD

GND

GND CKOUT

D1

VC3

IRQ

VC2

D0

PWROUT

GND

GND

RESET

PWRIN

VC2

VC2

A0

CLBD

VC2

WR

GND

X1

X2

VC2

GND

LFT

RD

CS

PDWN